Integrated circuit device having cyanate ester buffer coat and method of fabricating same

ABSTRACT

An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

This is a continuation of application Ser. No. 09/552,738, filed Apr.19, 2000, issued as U.S. Pat. No. 6,420,214, which is a continuation ofapplication Ser. No. 09/257,402 filed Feb. 25, 1999 (issued as U.S. Pat.No. 6,060,343), which is a divisional of Ser. No. 08/604,219 filed Feb.20, 1996 (issued as U.S. Pat. No. 5,903,046), which are all incorporatedherein by reference.

FIELD OF THE INVENTION

The present invention relates to an integrated circuit device and amethod of producing an integrated circuit device. More particularly, thepresent invention relates to an integrated circuit device having acyanate ester buffer coat and a method of producing the integratedcircuit device.

BACKGROUND OF THE INVENTION

Both high density and lower density integrated circuits are fabricatedon wafers utilizing numerous fabrication techniques, including, but notlimited to photolithography, masking, diffusion, ion implantation, etc.After the wafers are fabricated, with the wafer including a plurality ofintegrated circuit dies, a die coat is commonly used to protect theplurality of integrated circuit dies from damage during the remainder ofthe manufacturing process. It is commonly known to use polyimides as thebuffer or die coat when fabricating such devices or wafers.

Thermosetting resins, such as cyanate esters, have been used in variousapplications that span electronic, structural aerospace, and microwavetransparent composites as well as encapsulants and adhesives. Cyanateesters are described in the paper Arocy® Cyanate Ester Resins Chemistry,Properties and Applications, by D. A. Shimp, J. R. Christenson, and S.J. Ising (Second Edition—January 1990). Some examples of uses of cyanateesters include spinning cyanate ester onto a wafer for the purpose ofmaking a durable base for building electric conductive metal featuresand also circuit board configurations.

Polyimides utilized as a spin-on die coat are somewhat expensive. Manypolyimides have a high dielectric constant and do not cure very quickly.Cyanate esters on the other hand have a lower dielectric constant thanmost polyimides and further cure more quickly than polyimides. Inaddition, polyimide buffer coats do not have extremely consistentphoto-imageable characteristics. For example, when using photo-maskingor photolithography techniques with polyimides, such techniques are notalways highly successful or reliable. Therefore, in view of the above,there is a need for improved buffer coats for the fabrication processand improved integrated circuit devices resulting therefrom.

SUMMARY OF THE INVENTION

In accordance with the present invention, an integrated circuit includesa fabricated die having a cyanate ester buffer coating material thereon.The cyanate ester buffer coating material has one or more openings foraccess to the die. In another embodiment of the integrated circuit, diebond pads are connected to a die package device through such openings.

In accordance with another embodiment of the invention, the integratedcircuit device includes a fabricated wafer including a plurality ofintegrated circuits fabricated thereon. The fabricated wafer includes anupper surface having a cyanate ester buffer coating material curedthereon.

In a further embodiment, the cyanate ester coating material may be curedon a substantially planar or nonplanar surface of the fabricated die.Further, the upper surface of the fabricated wafer may be asubstantially planar or nonplanar surface.

In the method of the present invention, integrated circuit devices areproduced by providing a fabricated wafer including a plurality ofintegrated circuits. The cyanate ester coating material is applied andcured on a surface of the fabricated wafer.

In further embodiments of the method, the cyanate ester coating materialmay be spun on the surface of the fabricated wafer to form a buffercoat, the surface of the fabricated wafer may be a substantially planaror nonplanar surface, and/or the buffer coat may be a photosensitivebuffer coat.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of an integrated circuit wafer, as singulated, inaccordance with the present invention;

FIG. 2 is a sectional view of a part of an illustrative integratedcircuit in accordance with the present invention;

FIG. 3 is a flow diagram showing a process in which a buffer coat isapplied to the fabricated integrated circuit wafer of FIG. 1;

FIG. 4 is a flow diagram showing a process of interconnection ofindividual integrated circuit die having a buffer coat thereon to apackaging device; and

FIGS. 5A and 5B (collectively herein “FIG. 5”) are illustrations showingconnection an individual integrated circuit die of the wafer of FIG. 1to a packaging substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference to FIGS. 1 and 2, the integrated circuit device, or wafer10, including the individual integrated circuit dice 20 shall bedescribed. Integrated circuit device 10 of FIG. 1 is shown in aseparated or singulated state wherein the individual integrated circuitsor dice 20 are separated. The integrated circuit device or fabricatedwafer 10 includes on its top surface, in an unseparated state (notshown), a buffer or die coat 30 as shown in FIG. 2. The buffer or diecoat 30 is a cyanate ester coating material such as cyanate ester resinsavailable from Ciba Polymers, a division of Ciba-Geigy, having a placeof business in Hawthorne, N.Y.

The cyanate ester buffer coat 30 is applied to the fabricated integratedcircuit 21 to form the buffer coated integrated circuit device or wafer10, which includes the plurality of buffer coated individual integratedcircuits 20. The uncoated fabricated integrated circuit 21 of FIG. 2 isfabricated in accordance with typical integrated circuit fabricationtechniques, as are well known to one skilled in the art.

In FIG. 2, for illustration only, the integrated circuit 21 includessilicon substrate 25, field oxide elements 26 for isolation betweentransistors and polysilicon gates 28. Metalization 22 is fabricated overa doped oxide 27 which extends over the silicon substrate 25 and otherelements 26 and 28. Oxide 24 separates the metalization 22. As statedabove, the detail with respect to the integrated circuit 21 is shown forillustration purposes only, and the present invention is not limited tosuch configuration but only as described in the accompanying claims. Thepresent invention of the integrated circuit device or wafer 10 and theindividual circuits 20 including a cyanate ester buffer coat isapplicable to any conceivable circuit configuration of a fabricatedintegrated circuit 21 as would be readily apparent to one skilled in theart.

The metalization 22 includes bond pads 23 for connecting the individualintegrated circuit dies 20 to a packaging device or substrate as is wellknown to one skilled in the art. The cyanate ester buffer coatingmaterial 30 is applied to entirely cover the fabricated integratedcircuits 20, including bond pads 23. The cyanate ester buffer coatingmaterial forms the buffer coat 30 when dried or cured.

The integrated circuit 21, shown in FIG. 2, has a substantially planarsurface to be coated with the cyanate ester coating material 30.However, the cyanate ester coating material may be applied to non-planarfabricated integrated circuits as well as planar surfaces. In non-planarintegrated circuits or multi-layer circuits, the cyanate ester coatingmaterial will flow into the gaps or valleys between leads and the die.Because of the low dielectric characteristics of a cyanate ester coatingmaterial, capacitance between such leads will be reduced.

The cured cyanate ester coating material 30, as shown in FIG. 2, isformed from a cyanate ester resin, such as that available from CibaPolymers, a division of Ciba-Geigy Corporation under the tradedesignation of Arocy, such as AroCy M resins. These cyanate ester resinsare described in the publication “Arocy® Cyanates Ester ResinsChemistry, Properties, and Applications,” by D. A. Shimp, J. R.Christenson, and S. J. Ising (Second Edition—January 1990) hereinincorporated by reference thereto.

Cyanate esters are a family of thermosetting resins. Examples of cyanateesters are disclosed in U.S. Pat. Nos. 4,330,658, 4,022,755, 4,740,584,3,994,949, and 3,755,402, which are incorporated herein by reference.Preferably, suitable cyanate esters are those cured cyanate esters thathave low dielectric loss characteristics such as those having dielectricconstants in the range of about 2.0 to about 3.0 at 1 MHZ. Such suitableresins should have dimensional stability at molten solder temperatures,high purity, and excellent adhesion to conductor metals at temperaturesup to about 250° C. Cured cyanate ester coating materials, such as thoseavailable from Ciba-Geigy, have dielectric constants in the preferredrange. However, suitable cyanate ester coating materials with lowerdielectric constants and thus, low dissipation factors, are contemplatedin accordance with the present invention as described in theaccompanying claims. In addition, suitable cured cyanate ester coatingmaterial should be extremely durable and tough, having, for example, afree standing tensile elongation of about 2.5 to about 25%. Further, thecured cyanate esters should have a low tensile modulus in the range ofabout 1 to about 5 GPa and have a low H₂O absorption characteristic inthe range of about 0.5 % to about 3.0%. The resins should also beprocessable under the conditions of standard semiconductor manufacturingprocesses and stable under the conditions of processing such as spincoating, photolithography, development and curing. Moreover, the curedcyanate esters should have a low coefficient of thermal expansion in therange of about 20 to about 70 PPM/°C.

A particularly suitable group of cyanate ester resins are bisphenolderivatives containing a ring-forming cyanate functional group (i.e.,—O—C≡N) in place of the two —OH groups on the bisphenol derivatives.Generally, this family of thermosetting dicyanate monomers andprepolymer resins, are esters of bisphenol and cyanic acid whichcyclotrimerize to substituted triazine rings upon heating. Conversion orcuring to thermoset plastics forms three-dimensional networks ofoxygen-linked triazine rings and bisphenol units. Such networks aretermed polycyanurates. A preferred dicyanate monomer can be representedas follows:

wherein the bisphenol linkage (X) may be any of those commonlyincorporated into cyanate esters, such as —O—, —CH₂OCH₂—, —S—, —C(O)—,—O—C(O)—O—, —SO₂—, —S(O)—, as well as (C₁-C₂₀)alkyls,(C₅-C₁₈)cycloalkyls, (C₅-C₁₈)aryls, or —(R¹)C(R²)— wherein R¹ and R²independently represent H, a (C₁-C₄)alkyl group, or a fluorinated(C₁-C₄)alkyl group. Preferably, X is —S—, a (C₁-C₄)alkyl group, a(C₅-C₁₀)cycloalkyl group (including fused ring systems), —(R¹)C(R²)—wherein R¹ and R² are independently a (C₁-C₄)alkyl group or a perfluoro(C₁-C₄)alkyl group. More preferably, X is —(CH₃)C(CH₃)—, —CH₂—, —S—,—(CF₃)C(CF₃)—, or —(CH₃)CH— as listed in Table 2 of the publication“Arocy® Cyanates Ester Resins Chemistry, Properties, and Applications,”by D. A. Shimp, J. R. Christenson, and S. J. Ising (SecondEdition—January 1990). The ring substituent (R), which may be the sameor different, may be hydrogen, a (C₁-C₄)alkyl group, a (C₁-C₄)alkoxygroup, Cl, Br, or any other substituents typically incorporated incyanate esters. Preferably R is H or a (C₁-C₄)alkyl. More preferably, Ris H or CH₄, wherein the CH₄ groups are in the ortho position relativeto the cyanate groups.

Cyanate ester coating materials are available as dicyanate monomers andalso as partially cyclotrimerized dicyanate monomers or prepolymerresins from a number of sources. Cyanate ester prepolyner resins developcured state properties which are substantially identical to those of thecorresponding cured dicyanate monomers. Thus, the dicyanate monomers aswell as the cyclotrimerized prepolymer resins are suitable for use inthe present invention. Such materials are available from Ciba Polymers adivision of Ciba-Geigy Corporation. Dow Chemical Company, Mitsubishi GasChemical Company, and Hi-Tek Polymers.

The cured cyanate ester buffer coat 30, because of its durability, isparticularly useful in protection of the integrated circuits 21 afterfabrication. Such a cyanate ester buffer coat protects the integratedcircuits 21 even after singulation of the wafer 10 during themanufacturing process. As further described below with reference to FIG.4, the photoimageable characteristics of cyanate ester coating materialsare better than other die coats such as polyimides providing for moreconsistent photomasking and etching results. Cyanate ester coatingmaterials also cure faster as compared to polyimide die coats providingfor a faster coating process and, as a result, an increase in output ofintegrated circuit devices.

The buffer coating process for the integrated circuit devices shall bedescribed with reference to FIG. 3 and the process of connecting theindividual integrated circuit or individual die to a package deviceshall be described with reference to FIGS. 4 and 5. As shown in, FIG. 3,an uncoated fabricated integrated circuit device, such as a wafer,including circuits 21, is provided to initiate the process asrepresented by block 50. As indicated previously, any uncoatedfabricated integrated circuit device, whether having an upper surfacethat is planar or nonplanar, can be coated with a cyanate ester coatingmaterial as represented in block 52. The cyanate ester coating materialis spun onto the integrated circuit device or fabricated wafer as iswell known to one skilled in the art. Any other application techniquefor covering the upper surface of the integrated circuits 21 may besubstituted for the spinning technique. Such alternate techniques ofapplying the cyanate ester coating material may include, for example,die dispense, extrusion, screen printing, and spray coat.

As is well known to one skilled in the art, when spinning on a coatingmaterial such as cyanate ester coating material, the coating material isapplied on the wafer surface to be coated and the wafer is then spunsuch that the coating material is distributed over the wafer bycentrifugal force. The final thickness of the layer of coating materialon the wafer is based on, at least in part, the spin rate, the viscosityof the coating material, temperature, pressure, etc. The preferredthickness of the cyanate ester coating material applied on the wafer isin the range of about 1 micron to about 24 microns. More preferably, thethickness of the cyanate ester coating material is in the range of about5 microns to about 15 microns.

The spinning process can be carried out in numerous different steps. Forexample, the coating material can be dispensed on the wafer while thewafer is standing still and then the speed is increased to a particularspeed for distributing the material over a period of time. Any number ofintermediate spinning steps could be utilized such as going from standstill to an intermediate speed for a particular period of time and thenfurther increasing the spinning speed. It will be readily apparent thata multitude of spinning parameters are contemplated in accordance withthe present invention as described in the accompanying claims. Thespinning process can be carried out with any number of different spincoating systems.

After the cyanate ester coating material is applied and processed as isknown to one skilled in the art, the coating material is cured asrepresented in block 54. Curing is performed in a furnace or by someother heating unit. The cyanate ester coating material may be cured at atemperature in the range of about 250-290° C. The curing process mayvary in temperature or duration and the curing process for the cyanateester resins provided from the various manufacturers may differ greatly.The curing process may also take place in a number of differentatmospheres, including air, nitrogen, or other forming gases. Suchcuring may also be done under pressure or with some sort of curingcatalyst. Further, the cured cyanate ester buffer coat may be machined,ground or milled, if desired, to a specific thickness, such as bychemical mechanical polishing or planarization (CMP).

The connection of buffer coated individual integrated circuits 20 of thewafer 10 to packaging devices, such as package substrates, can beaccomplished in accordance with the procedure of FIG. 4. The buffercoated wafer 10 is provided from the process described with reference toFIG. 3 and as represented by block 60. The bond pads 23 of the variousindividual integrated circuits 20 may be opened to access the bond padsas represented in block 62. One or more openings in the buffer coat aremade using photo-masking and etching as is known to one skilled in theart. A photo resist is applied to the wafer, and the desired pattern ofthe photo resist is polymerized by ultraviolet light through a photomask. The unpolymerized areas are removed and an etchant is used to etchthe buffer coat 30 to form the one or more openings. One opening in thebuffer coat may provide access to one or more die bond pads. The photoresist remaining is then removed as is known to one skilled in the art.The one or more openings may be of any size or shape. Further, the oneor more openings may provide access to the die for purposes other thanconnection to packaging devices, for example, such access to the die maybe utilized for repair, test, etc.

Cyanate ester coating material may also be converted to a photosensitivebuffer coat by the addition of photosensitive ingredients, e.g. aphotoactive compound (PAC). This would reduce the number of processsteps for opening the buffer coat to access the fabricated wafer underthe buffer coat.

As represented by block 64, the individual integrated circuits 20 areseparated or singulated by techniques as known to one skilled in theart, such as etching, sawing, or scribing with a stylus or laser, andthen breaking the wafer apart into small squares or rectanglescomprising the individual integrated circuits 20. Any of individualcircuits can be connected to a packaging device or substrate which mayinclude a lead frame, or some other device for connecting the bond pads23 of the integrated circuit device 21 to the packaging device orsubstrate. The connection is illustrated in FIG. 5 and is represented byblock 66 of FIG. 4.

FIGS. 5A and 5B show two configurations of mounting die to a packagingsubstrate. Such configurations are described for illustrative purposesonly as the invention is limited only by the accompanying claims. Manyother connection techniques are known to those skilled in the art andfall within the scope of the accompanying claims.

FIG. 5A illustrates a wire bonding connection. An individual integratedcircuit 20 is attached to a substrate or base 34 such as a lead framevia adhesive 36. The integrated circuit 20 includes the cyanate esterbuffer coat 30 with openings in the buffer coat over the bond pads 23created as per block 62. The bond pads 23 are then connected by leads 38to metalization on substrate 34.

FIG. 5B illustrates a flip TAB face down connection. An individualintegrated circuit 20 is attached to a substrate or base 34 via adhesive36. The integrated circuit 20 includes the cyanate ester buffer coat 30with openings in the buffer coat over the bond pads 23 created as perblock 62. The bond pads 23 are then connected by tape leads 70 tometalization on substrate 34. FIGS. 5A and 5B illustrate only two typesof package interconnection and other types, such as additional TABbonding, flip bonding, or other interconnection methods may be used asalternatives.

The cyanate ester buffer coat 30 buffers the stress buildup in a packagedue to mismatching coefficients of thermal expansion. For example, withbond pads interconnected to the substrate using the flip TABconfiguration of FIG. 5B with a filler (not shown) utilized next to thebuffer coat 30, if coefficients of thermal expansion between the fillerand the buffer coat are not matched to within some predetermined limits,stress on the leads develops in the package containing the integratedcircuit 20. The characteristics of the cyanate ester buffer coat 30,because of its compatible coefficients of thermal expansion tosubstrates, relieves substantial stress in such and like configurationswhere mismatch of the coefficients would create such stress. Further,the device mounted on a lead frame may be packaged by an encapsulant(not shown) about the buffer coat 30 of FIG. 5A to form the package,such as a DIP package. If the coefficients of expansion between theencapsulant and the buffer coat is mismatched, stress may develop in thepackage. The characteristics of the cyanate ester buffer coat 30,because of its compatible coefficients of thermal expansion toencapsulants, such as Sumikon 6300, available from Sumitoma Bakelite,JP, relieve substantial stress in such packages where mismatch of thecoefficients would create such stress inside the package.

Although the invention has been described with particular reference to apreferred embodiment thereof, variations and modifications of thepresent invention can be made within a contemplated scope of thefollowing claims as is readily known to one skilled in the art.

What is claimed is:
 1. An integrated circuit die package, the packagecomprising: an integrated circuit comprising: a fabricated diecomprising one or more die bond pads; and a cyanate ester buffer coatingmaterial comprising a cyanate ester resin on a surface of the fabricateddie, wherein the cyanate ester buffer coating material further comprisesone or more openings for access to the fabricated die; a die packagestructure electrically connected to the one or more die bond pads of thefabricated die via the one or more openings of the cyanate ester buffercoating material; and an encapsulant about at least a portion of thecyanate ester buffer coating material, wherein the encapsulant comprisesa coefficient of thermal expansion selected to match the coefficient ofthermal expansion of the cyanate ester buffer coating material.
 2. Thepackage of claim 1, wherein the die package structure is electricallyconnected to the one or more die bond pads of the fabricated die viawire leads.
 3. The package of claim 1, wherein the die package structureis electrically connected to the one or more die bond pads of thefabricated die via tape leads.
 4. The package of claim 1, wherein thecyanate ester buffer coating material comprises a thickness in a rangeof about 1 micron to about 24 microns.
 5. The package of claim 4,wherein the cyanate ester buffer coating material comprises a thicknessin a range of about 5 microns to about 15 microns.
 6. An integratedcircuit die package, the package comprising: a substrate comprising atleast one metallization region; an integrated circuit attached to thesubstrate, the integrated circuit comprising: a fabricated diecomprising one or more die bond pads; a cyanate ester buffer coatingmaterial comprising a cyanate ester resin on a surface of the fabricateddie, wherein the cyanate ester buffer coating material further comprisesone or more openings for access to the one or more die bond pads of thefabricated die; and an encapsulant about at least a portion of thecyanate ester buffer coating material, wherein the encapsulant comprisesa coefficient of thermal expansion selected to match the coefficient ofthermal expansion of the cyanate ester buffer coating material; whereinthe one or more die bond pads of the fabricated die are electricallyconnected to the at least one metallization region of the substrate viathe one or more openings of the cyanate ester buffer coating material.7. The package of claim 6, wherein the at least one metallization regionof the substrate is electrically connected to the one or more die bondpads of the fabricated die via wire leads.
 8. The package of claim 6,wherein the at least one metallization region of the substrate iselectrically connected to the one or more die bond pads of thefabricated die via tape leads.
 9. The package of claim 6, wherein thecyanate ester buffer coating material comprises a thickness in a rangeof about 1 micron to about 24 microns.
 10. The package of claim 9,wherein the cyanate ester buffer coating material comprises a thicknessin a range of about 5 microns to about 15 microns.